A data processing system wherein messages are transferred between users through a shared memory is described in EP-A-0 365 731.
This system is based on a specific memory organization and hardware assist circuits which facilitates the memory queue management.
The memory comprises a linear space and a buffer-organized space. Each page of the buffer-organized space is divided in a number m+1 of buffers of equal capacity, with m buffers devoted to the storage of message data and one control buffer divided into m control blocks. There is a fixed relationship between each buffer control block and each data buffer. The control blocks are dedicated to the storage of buffer and message chaining information.
The linear space comprises queue control blocks. The messages are received from the source users and enqueued in inbound queues which are dynamically built by taking buffers from the buffer-organized space, chaining the buffers by writing buffer and message chaining information in the corresponding buffer control blocks, and writing the queue head and queue tail addresses in the corresponding queue control blocks.
A centralized control circuit is designed to process lease, enqueue, dequeue and release orders upon requests from a user selected by an arbiter.
When an inbound queue of a source user becomes not empty, a receive hardware assist circuit sends a dequeue order request to the centralized control circuit, the dequeue order request identifying the corresponding queue control block. The message address is provided in response thereto with the identification of the queue control block of the destination user.
Then, the receive hardware assist circuit sends an enqueue order request to the centralized control circuit, said request identifying the address of the message to be enqueued and the queue control block of the destination user. The processing of this enqueue request by the centralized control circuit causes the messages to be enqueued to an outbound message queue. They are transmitted to the destination user by a transmit hardware assist circuit.
The free buffers of the buffer-organized space constitute a free buffer queue in which the buffers are chained via their buffer control blocks, the free buffer queue having a queue control block which contains the addresses of the queue head and queue tail. Buffer addresses are provided to a user in response to a lease order request.
There are different types of users such as hardware users which are communication adapters receiving/transmitting messages from/to communication links and at least one software user which comprises a microprocessor for processing the messages, i.e. performing the message routing or other operations. In case of any malfunction, the hardware users or software user may lose the control of buffers.
Each buffer or set of buffers is owned at a given time by a user. If there were only software users, one solution to recover the lost buffers would consist of keeping track of the users to which buffers are allocated and recovering the associated buffers in case of failure of a user.
This solution is valid in a software environment. It cannot be implemented in the environment previously described for performance reasons, because the control microcode which keeps track of the buffer allocations would have to be aware of all message transfers and of all buffer lease and release operations.